Soldering is a well known process for forming electrical connections between electronic components such as semiconductor chips, chip carriers, modules, resistors, capacitors, etc. and the electrically conductive pads (or sites) on the external surface of circuitized substrates such as printed circuit boards and chip carriers. Several different forms of such processes have evolved over the years, including, e.g., wave soldering wherein a printed circuit board, populated with such components, is passed over a crest of a molten solder wave, immersion wave soldering in which a conventional solder wave submerged in a heated flux bath is utilized, and vapor phase reflow soldering which utilizes the latent heat of vaporization stored in a saturated vapor of inert fluorinated organic compounds (e.g., Fluorinert). Additional description of various solder processes is provided herein-below.
Today's electronics industry demands many products, particularly those utilizing circuitized substrates, to be of smaller size, as the trend toward smaller components and higher integration densities of integrated circuits continues. Customers want smaller computers, calculators, printers, telephones, etc., all with increased functional capabilities. To meet these demands, manufacturers of circuitized substrates must develop new processes for the successful (quick, relatively inexpensive, and adaptable to mass production) application of solder to extremely small areas and in carefully controlled volumes. To make such processes all the more complex, the resulting connections must not be so close as to allow solder “bridging” between adjacent connections.
One widely used technique, particularly for direct attachment of a semiconductor chip, chip carrier or like components onto a board or module, is surface mount technology. One form of such technology utilizes what are referred to as solder “pre-forms”, possibly including a desired flux, for application to locations where solder connections are to be made. Such pre-forms are formed (solidified) solder elements which are positioned on the designated substrate pads and which are then heated (re-flowed) once the components are in place, until solidification once again occurs and the final couplings (connections) realized. Use of solder pre-forms has proven relatively successful for forming solder connections at small sizes and close spacings since the volume of solder contained in each pre-form can be controlled in a relatively accurate manner. However, the minimum size of such pre-forms is limited to sizes which can be efficiently handled by automated placement equipment and does not answer current needs for many electronic package manufacturing applications.
Another known process is the use of pulverized solder material in a viscous binder in the form of a paste which can be applied by stenciling. While this process has been largely successful in applying solder to locations having sizes and spacings smaller than those where solder pre-forms are used, the accuracy with which the dispensed volume of solder can be controlled is limited by the stenciling process utilized. Because of the relatively harsh (primarily high temperatures) conditions associated with soldering, stenciling presents drawbacks due to the possibility of contamination, wear and damage to the stenciling masks through which the paste is extruded. Irregular solder paste deposition can result in one or more connections not being achieved, resulting in possible scrapping and/or re-working of the completed final product (e.g., a printed circuit board having several components mounted thereon), a very costly and therefore undesirable result. Irregularities of solder paste distribution may also be caused by the separation of the stencil mask from the substrate surface onto which the solder paste is being deposited. Still further, the minimum size of particles used for the solder material which can be formed is limited by the process by which the particles themselves are formed. That is, particles of smaller size are typically formed by atomization and solidification of liquid solder, causing an increase in the ratio of surface area-to-volume as size decreases, in turn causing an increase in oxide-to-metal volume for a fixed thickness of oxide on the surface of the particle and a greater viscosity of the paste for a given metal loading of the paste having the particles. Lowering metal loading and viscosity, in turn, requires a thicker stencil to obtain the desired volume of metal with higher aspect ratio openings, which is contrary to the normal and desirable operating requirements for stencils in order to accommodate small feature sizes since high aspect ratio stencil openings (and high viscosity) reduce the ability of the paste to release from the stencil. Thus, there is a trade-off between process complexities and requirements which limits the deposit size and stenciling resolution which can be achieved and control of the locations to which either the paste or the solder, itself, may flow. Still further, solder stenciling processes and the processes for fabrication of masks through which stenciling is done do not support the close spacing or fine pitch of solder connection locations which can be formed by photo-lithographic technologies which are typically utilized as part of the circuit defining process. Registration of the mask with connection locations also becomes difficult when extremely close spacing of connections is required.
It is also known that, in the process of making a solder connection to a copper conductor (copper being one of the most widely used metals for substrate pads, lines, etc of a substrate's circuit pattern), some copper is typically removed from the pad and becomes part of the solder connection material. This may become critical in some applications in microelectronic manufacturing, particularly in devices which are subjected to high temperature operation and thermal cycling, since tin-copper inter-metallic compound precipitates may be formed (that is, when tin is part of the solder composition as is also well known for most solders). Further, the solubility of copper in typical solder materials is very small and on the order of 0.3%. Therefore, most excess copper in the solder materials will be in the form of such inter-metallic compounds. Inappropriate amounts of copper in the solder material may degrade the reflow characteristics of the solder. Specifically, when conductors are closely spaced, it is desirable that the solder “pulls back” toward the conductor (pad) on which the connection is made and away from adjacent conductors. This action also maximizes the conductive material in the connection and provides for a stable configuration of the solder material even when softened by normal or abnormal temperatures after the final substrate product is put into service (e.g., as part of a computer). Such reflow may also be adversely affected by small amounts of copper on the surrounding substrate, allowing such areas to be partially wetted or bridged. Perhaps the best solution known at the present time is to dissolve such copper deposits in the solder (which is often difficult due to the relatively low solubility of copper in solder materials, especially when the conductor also provides a source of copper solute in the solder material), is to react the copper from the solder with other materials, or use aggressive fluxes. These “solutions” typically mandate longer reflow times and may even compromise the integrity of the resulting, formed solder connection. Other materials, such as gold, are also known to have low solubility in solder and exhibit similar adverse effects on solder connections and reflow. One particularly desirable aspect of the instant invention is that it is capable of forming solder couplings in which some tin and/or copper from the site may be incorporated within the solder composition in satisfactory amounts which will not adversely affect the resulting connections formed.
In U.S. Pat. No. 4,487,654 (Coppin), there is described a method of manufacturing a printed circuit board utilizing a solder mask over bare copper for circuit traces and ground planes. The method includes the step of electroplating a very thin coating of tin-lead over the circuit traces, ground planes, holes and circuit pads prior to selectively coating only the pads and holes with a relatively thick coating of tin-lead solder plate. After removing the plating resist which defines the areas for selective solder coating, the board is chemically etched and then mechanically scrubbed to roughen the surface of and reduce the thickness of the thin solder plate. A solder mask may be applied over circuit traces and ground planes prior to reflowing the thick coating of solder plate. Assembled printed circuit boards are then wave soldered.
In U.S. Pat. No. 4,745,004 (Schwerin), there is described a method and apparatus for transporting work through a series of work processing stations by moving the work along a path extending past the stations to successive positions along the path opposite the stations, respectively, and at each position extending and retracting the work into and from the respective station for processing of the work therein. The method and apparatus are designed to coat or plate the conductors and thru-holes of printed circuit boards with solder by mounting the circuit boards in rack-like work holders, transporting the work holders in succession from an feed station to a release station along a path extending over a series of tanks containing liquid baths of acid, rinse solution, flux, solder/oil and final wash, respectively, and extending and retracting each work holder downwardly into and upwardly from each tank to successively clean, rinse, flux, solder coat and wash the circuit boards.
In U.S. Pat. No. 4,958,588 (Hutchison et al), there is described an apparatus (fixture) for solder-coating respective end portions of elongated components in a molten solder bath. This fixture includes a supporting wall capable of maintaining the fixture afloat on an upper surface of the molten solder bath when the fixture is fully loaded. The supporting wall has an opening through which one of the end portions of a component passes into the molten solder bath to a depth necessary for the molten solder to coat the respective end portion to the desired extent. The fixture may be used in conjunction with a handling device which advantageously includes two pin-shaped projections that engage the fixture at two locations spaced along a horizontal axis with freedom of movement of the fixture relative to the projections at least in the upward direction in that the projections are received in respective vertical slots of the fixture. These projections are then moved at least downwardly to an extent necessary to lower the fixture onto the upper surface of the molten bath and then release the fixture for free floating on the upper surface of the molten solder bath.
In U.S. Pat. No. 4,978,423 (Durnwirth, Jr. et al), there is described a method of providing solder on selected portions of a printed circuit board. Solder is first electroplated over copper conductor patterns on the board by means of a first photoresist layer. After stripping the first photoresist, a second photoresist layer is laminated over the board and developed to expose selected portions of the solder. The exposed portions are selectively stripped. The copper exposed by the selective stripping is then subjected to a scrubbing while the photoresist protects the remaining solder. The second photoresist is then removed.
In U.S. Pat. No. 5,130,164 (Hutchison et al), there is described a method for solder-coating respective end portions of elongated components in a molten solder bath. This method includes maintaining a fixture afloat in a predetermined position on an upper surface of a molten solder bath when the fixture is fully loaded. End portions of a respective component pass into the molten solder bath to a depth necessary for the molten solder to coat the portions to the desired extent. This patent is a divisional of U.S. Pat. No. 4,958,588 above.
In U.S. Pat. No. 5,398,865 (Mittag), there is described an apparatus and process which prepares surfaces on components, boards and the like for assembly and solder joining. Oxides and other coatings are removed from the surfaces to be soldered without having to solder coat the surfaces prior to joining. A composition of a polymer and an activator is applied to the surfaces, the polymer being thermally de-polymerizable. The composition claims to remove oxides from the surfaces. The surfaces are heated after application of the polymer and activator to de-polymerize the polymer. Solder is then applied to solder join the surfaces.
In U.S. Pat. No. 5,597,469 (Carey et al), there is described a process in which small, closely spaced deposits of solder materials may be formed by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching, and thereafter reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Fluid jet sparging and cathode agitation are also utilized. Excess conductor material in the resulting solder deposit is allegedly avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to the electroplating step of the process.
In U.S. Pat. No. 5,672,260 (Carey et al), a continuation of U.S. Pat. No. 5,597,469 above, there is described method of forming solder deposits on a solder wettable material which includes the steps of electroplating solder materials onto portions of a conductive layer on a first layer of non-solder wettable material having apertures therein and covering a portion of the solder wettable material. Portions of the conductive layer are exposed during the electroplating by additional apertures in a second layer of non-solder wettable material, these additional apertures having dimensions sized to define a volume of solder material to be deposited by the electroplating step. The deposited solder materials are then reflowed away from a portion of the surfaces of the first layer of non-solder wettable material.
In U.S. Pat. No. 5,863,812 (Manteghi), there is described a method for fabricating a chip size package which includes the step of forming a laminated substrate which consists of a dielectric layer and a highly conductive layer disposed thereon. Holes are drilled into the dielectric layer. A desired pattern is applied to the conductive layer. A chip structure is formed which consists of a silicon die and an insulating layer disposed thereon. Gold bumps are applied to the top surface of the bonding pads. The laminated substrate is bonded to the chip structure via the holes and gold bumps. A solder mask is applied over the top surface of the conductive layer of the laminated substrate so as to form selective solder areas. Finally, solder balls are attached to the selective solder areas.
In U.S. Pat. No. 5,873,511 (Shapiro), the placement of solder “balls” in a ball grid array package is accomplished by placing a solder strip in contact with the top surface of the ball grid array carrier. The pulsing of a laser directed at the solder in discrete positions permits the transfer of the solder to the gold “dot”, of an array of “dots”, on the carrier in registry with the laser output when activated. Selective solder placement is possible and increasingly higher throughput is achieved by the use of laser diode bars or optical fiber fans to effect solder transfer to a plurality of dots of the array simultaneously. The entire process is described as capable of being automated by making the solder strip continuous through a recycling station arranged along a path along which the solder strip moves to the position where the carrier and the solder strip are moved into juxtaposition. The use of a transparent strip with a pattern of holes filled with solder paste permits easy transfer of the solder to the gold dots or islands on the carrier in registry with laser beam.
In U.S. Pat. No. 6,022,466 (Tamarakin et al), there is described a process for plating gold on a multi-layered printed circuit board. In one embodiment, first copper features for plating gold thereon and second copper features for plating copper thereon are selected on the board's external surface. The first copper features are internally connected to the second copper features. An etch-resist on the first and second copper features is deposited. The second copper features are masked, while a region containing the first copper features is exposed. Copper from the region is etched. The etch-resist on the first copper features is removed. Gold is then plated on the first copper features.
In U.S. Pat. No. 6,044,550 (Larson), there is described process for producing printed circuit boards which utilizes the steps of drilling holes in a copper clad laminate, applying an imaged etch resist to an outer surface of the copper clad laminate, contacting the copper clad laminate with an etchant for copper to create circuit “elements” on the copper clad laminate having the imaged etch resist applied thereon, activating the holes to accept plating therein, stripping away the imaged etch resist, applying an imaged plating mask to the surface of the copper clad laminate, and contacting the copper clad laminate with a plating solution which plates a metal coating in the holes.
In U.S. Pat. No. 6,586,683 (Arrington), there is described method of fabricating a printed circuit board which includes an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate. The method includes forming an oxide layer on one set of conductors, forming a solder mask on the oxide layer, forming a composite layer on another set of conductors, and forming a solder layer on at least a portion of the remaining set of conductors. A commoning bar is used as part of the method. The patent mentions that the conductors may be of different metallurgies.
In U.S. Pat. No. 6,378,199 (Yoshinuma), there is described a multi-layer printed-wiring board including a substrate having a plurality of wiring pattern layers sequentially transferred thereon, each wiring pattern layer containing an electrically conductive layer and an electrically insulating layer. The wiring pattern layers are attached to the substrate through an electrically insulating layer.
In U.S. Pat. No. 6,645,841 (Kever), there is described the selective application of solder “bumps” in an integrated circuit package. These solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied either to a die or to the substrate using multiple solder masks, one for each pattern of solder bumps desired, or these can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.
As will be understood from the following, the present invention provides a new and unique process for making circuitized substrates such as chip carriers and printed circuit boards in which a singular conductive layer serves as a commoning layer for the plating of solder onto two different conductor (namely pads and thru-holes) metallurgies in two separate steps, thereby eliminating the need for additional steps to provide dual plated solder applications while assuring optimal solder metallurgical matching for corresponding conductor metallurgies.
It is believed that such a process represents a significant advancement in the circuitized substrate art.